{"id":9243,"date":"2022-05-02T00:00:00","date_gmt":"2022-05-02T00:00:00","guid":{"rendered":"https:\/\/www.nextias.com\/current_affairs\/uncategorized\/02-05-2022\/design-linked-incentive-dli-scheme\/"},"modified":"2022-05-02T00:00:00","modified_gmt":"2022-05-02T00:00:00","slug":"design-linked-incentive-dli-scheme","status":"publish","type":"post","link":"https:\/\/www.nextias.com\/ca\/current-affairs\/02-05-2022\/design-linked-incentive-dli-scheme","title":{"rendered":"Design Linked Incentive (DLI) Scheme"},"content":{"rendered":"<p><span style=\"font-size:13pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong><u>In Context<\/u><\/strong><\/span><\/span><\/span><\/p>\n<ul>\n<li style=\"list-style-type:disc\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">The government will review norms of the <\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>Design Linked Incentive (DLI) program <\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">which envisages to <\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>support 100 companies<\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"> involved in product design in the semiconductor space as part of a Rs<\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong> 76,000 crore scheme <\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">for developing the electronic chip ecosystem in the country,\u00a0<\/span><\/span><\/span><\/li>\n<\/ul>\n<p><span style=\"font-size:13pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong><u>About<\/u><\/strong><\/span><\/span><\/span><span style=\"font-size:13pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><u> <\/u><\/span><\/span><\/span><span style=\"font-size:13pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong><u>Design Linked Incentive (DLI) Scheme<\/u><\/strong><\/span><\/span><\/span><span style=\"font-size:13pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>.<\/strong><\/span><\/span><\/span><\/p>\n<ul>\n<li style=\"list-style-type:disc\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">It was announced in December 2021 by MeitY.<\/span><\/span><\/span><\/li>\n<li style=\"list-style-type:disc\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">It aims to provide <\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>financial and infrastructural support<\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"> to companies setting up fabs or semiconductor making plants in India.<\/span><\/span><\/span><\/li>\n<li style=\"list-style-type:disc\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>Aims<\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">: To create a vibrant ecosystem for <\/span><\/span><\/span><a href=\"https:\/\/www.nextias.com\/current-affairs\/16-12-2021\/program-for-development-of-semiconductors-and-display-manufacturing-ecosystem-in-india\" style=\"text-decoration:none\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#1155cc\"><strong><u>Semiconductor Chip Design<\/u><\/strong><\/span><\/span><\/span><\/a><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"> in the country.<\/span><\/span><\/span><\/li>\n<\/ul>\n<ul>\n<li style=\"list-style-type:disc\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">To promote the domestic manufacturing of semiconductors and allied devices.\u00a0<\/span><\/span><\/span><\/li>\n<li style=\"list-style-type:disc\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">The scheme is expected to provide a globally competitive incentive package to companies in semiconductors and display manufacturing as well as design.<\/span><\/span><\/span><\/li>\n<\/ul>\n<ul>\n<li style=\"list-style-type:disc\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>Components<\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">: It has three components which are:\u00a0<\/span><\/span><\/span>\n<ul>\n<li style=\"list-style-type:circle\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>Chip Design infrastructure support:<\/strong><\/span><\/span><\/span>\n<ul>\n<li style=\"list-style-type:square\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">Under it, C-DAC will set up the India Chip Centre to host the state-of-the-art design infrastructure (viz. EDA Tools, IP Cores and support for MPW (Multi Project Wafer fabrication) &#038; post-silicon validation) and facilitate its access to supported companies.<\/span><\/span><\/span><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<ul>\n<li style=\"list-style-type:circle\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>The Product Design Linked Incentive:<\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">\u00a0<\/span><\/span><\/span>\n<ul>\n<li style=\"list-style-type:square\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">Under it, reimbursement of up to<\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong> 50% of the eligible expenditure <\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">subject to a ceiling of ?15 Crore per application will be provided as fiscal support to the approved applicants who are engaged in semiconductor design.<\/span><\/span><\/span><\/li>\n<\/ul>\n<\/li>\n<li style=\"list-style-type:circle\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>The Deployment Linked Incentive:\u00a0<\/strong><\/span><\/span><\/span>\n<ul>\n<li style=\"list-style-type:square\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">Under it, an<\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong> incentive of 6% to 4% <\/strong><\/span><\/span><\/span><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\">of net sales turnover over 5 years subject to a ceiling of ?30 Crore per application will be provided to approved applicants whose semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems &#038; IP Cores and semiconductor linked design are deployed in electronic products.<\/span><\/span><\/span><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#000000\"><strong>Source: <\/strong><\/span><\/span><\/span><a href=\"https:\/\/telecom.economictimes.indiatimes.com\/news\/govt-to-review-design-linked-incentive-scheme-mos-it-rajeev-chandrasekhar\/91233567\" style=\"text-decoration:none\" target=\"_blank\" rel=\"noopener\"><span style=\"font-size:12pt\"><span style=\"font-family:'Book Antiqua',serif\"><span style=\"color:#1155cc\"><strong><u>ET<\/u><\/strong><\/span><\/span><\/span><\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>In Context The government will review norms of the Design Linked Incentive (DLI) program which envisages to support 100 companies involved in product design in the semiconductor space as part of a Rs 76,000 crore scheme for developing the electronic chip ecosystem in the country,\u00a0 About Design Linked Incentive (DLI) Scheme. It was announced in [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":9244,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[21],"tags":[107,62,26,106],"class_list":["post-9243","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-current-affairs","tag-employment","tag-growth-development","tag-gs-3","tag-mobilization-of-resources"],"acf":[],"jetpack_featured_media_url":"https:\/\/wp-images.nextias.com\/cdn-cgi\/image\/format=auto\/ca\/uploads\/2023\/07\/4913759Screenshot_6.png","_links":{"self":[{"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/posts\/9243","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/comments?post=9243"}],"version-history":[{"count":0,"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/posts\/9243\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/media\/9244"}],"wp:attachment":[{"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/media?parent=9243"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/categories?post=9243"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.nextias.com\/ca\/wp-json\/wp\/v2\/tags?post=9243"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}